In reply to atanu.biswas:
Hi All,
I want to pass an entire interface from my testbench’s top module to the checker…endchecker block. Is it possible to do so?
You need to read 1800’2017 17.2 Checker declaration
checker checker_identifier [ ( [ checker_port_list ] ) ] ;
{ { attribute_instance } checker_or_generate_item }
endchecker [ : checker_identifier ]
checker_port_list ::= // from A.1.8
checker_port_item {, checker_port_item}
checker_port_item ::=
{ attribute_instance } [ checker_port_direction ] property_formal_type formal_port_identifier
{variable_dimension} [ = property_actual_arg ]
property_port_item ::=
{ attribute_instance } [ local [ property_lvar_port_direction ] ] property_formal_type
formal_port_identifier {variable_dimension} [ = property_actual_arg ]
// What this says is that in an checker, Interfaces and wires are NOT in the formal argument
// Also, per 1800
"Modules, interfaces, programs, and packages shall not be declared inside checkers. Modules, interfaces, and programs shall not be instantiated inside checkers."
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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