In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks a lot for confirming this. I have one more query. In my checker block I am having a UVM RAL based functionality. The code is as follows:
Checker block code:
checker reg_check(input string reg_name);
logic [31:0] address;
logic write_cycle;
initial begin
top.reg_temp = top.ral_inst.get_reg_by_name(reg_name);
address = top.reg_temp.get_address();
end
assign write_cycle = (top.mst_p.PADDR = address) && top.mst_p.PWRITE && top.mst_p.PENABLE && top.mst_p.PSEL;
endchecker
Top module code:
module top;
reg_block ral_inst;
uvm_reg reg_temp;
initial begin
ral_inst = reg_block::type_id::create(“ral_inst”);
ral_inst.build();
ral_inst.compare;
end
//Checker instance
reg_check rg3 (“register_name”);
endmodule
The issue is that I am getting a warning which reads:
**** Warning: (vsim-2974) Cannot find checker decl ‘reg_check’ for checker instance rg3**
Although the checker is working completely fine.