How to pass an interface in checker.. endchecker block argument?

SystemVerilog
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9

In reply to ben@SystemVerilog.us:

Hi Ben,

I have a doubt. The image says that assign statement cannot be used inside a checker body. But I have used an assign statement inside my checker block out of sheer curiosity to check how it behaves or what kind of error it throws. But surprisingly its working fine. Below is the code:

checker reg_check ( input logic [31:0] address );

logic write_cycle;

assign write_cycle = (top.mst_p.PADDR = address) && top.mst_p.PWRITE && top.mst_p.PENABLE && top.mst_p.PSEL;

endchecker

The toggling of the write_cycle is happening correctly.