In reply to atanu.biswas:
The following works
let MSB=3; let LSB=0;
let DEPTH=8;
let FIFO_MSB = DEPTH*MSB;
let FIFO_LSB = LSB;
checker generic_fifo
// #(MSB=3, LSB=0) // ILLEGAL
(input bit [MSB:LSB] in,
input bit clk, read, write, reset,
output logic [MSB:LSB] out,
output logic full, empty );
//parameter DEPTH=4; //ILLEGAL
endchecker
BTW, from my SVA book, The following table provides an overview of where checkers are declared, used, and their contents.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment