In reply to atanu.biswas:
In reply to ben@SystemVerilog.us:
Thanks for suggesting that. I need to create multiple instance of the checker in my top module and for each instance the parameter is different. Can the let variable be overridden as was the case with parameters?
See 1800’2017 11.12 Let construct
One fast way to verify the legality of construct is to try it using a simulator; hopefully, the tool undestands the syntax better than we do :).
Redeclaring the let defintion in the same context (e.g., in the same module) is illegal.
Also is it legal to assign an input formal argument of the checker to the let variable as shown below?
checker ( input bit [3:0] no_of_bits_to_compare );
let WIDTH = no_of_bits_to_compare;
endchecker
The “WIDTH” is going to be used in an assertion property.
This looks very convoluted and hard to follow. Looks like you want to define a let_definition to a checker variable that can dynamically change in value during simulation. You then want to use that definition as a range value in an assertion. ranges and repeasts in properties have to be static, and cannot be dynamic.
Question: Why are you using a checker? If the assertions defined in a checker are instantiated in-place within a module (i.e., are not instantiated inside an always block in the module), then you might as well use module instead of checker.
Since the instantiated verification modules should not be synthesized, use the NO_SYNTHESIS pragma around that instantiation. Check the syntax for the pragma.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment