How to generate 7 consecutive ones for "rand bit [31:0]:" data variable . Assuming the 7 consecutive ones can occur anywhere in the 32bits

SystemVerilog
,
1

Is there any constraint to do this.

2

I would do something like;

 constraint c { data == (7’b1111111 << N ); }

And constrain N to keep the shift inside the range of data.

3

I would try this

rand bit [31:0] data;
rand bit n,m ;  
constraint c{ data[n:m]== 7'd127; } 
constraint range { n <=31 ; n>=7 ; m == n-7 ; }
4

In reply to Shilton_uday:

data[n:m] where n and m are variables is not legal SystemVerilog syntax

1 Like
5

In reply to dave_59:

I tried following code but I am seeing an issue .

Code
class mem_seq_item extends uvm_sequence_item;
//Control Information
rand bit [31:0] data;
rand bit N;
//Utility and Field macros,
uvm_object_utils_begin(mem_seq_item) uvm_field_int(data,UVM_ALL_ON)
uvm_field_int(N,UVM_ALL_ON) uvm_object_utils_end

//Constructor
function new(string name = “mem_seq_item”);
super.new(name);
endfunction

//constaint, to generate any one among write and read
constraint c { data == (7’b1111111 << N ); }

constraint addr_1_range { N inside {[31:0]}; }
endclass

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;

//instance
mem_seq_item seq_item_0;

initial begin
//create method
seq_item_0 = mem_seq_item::type_id::create(“seq_item_0”);

seq_item_0.randomize(); //randomizing the seq_item   
seq_item_0.print();     //printing the seq_item_0

end
endmodule

output

Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 23: token is ‘\037777777742’
constraint c { data == (7\037777777742\037777777600\037777777631b1111111
<< N ); }

6

In reply to ritheshraj:

I try it too.

class Ctrans;
    rand bit[31:0] data;
    rand int N;
    constraint c{data==(7'b1111111 << N);
                 N<32-7;N>=0;}
endclass
module test_top;
    Ctrans trans;
initial begin
    trans=new();
    trans.randomize();
    $display("%b",trans.data);
end
endmodule

This is right.The message printed is “00000000000001111111100000000000”.
I think your constraint of N should be :

N inside {[0:31-7]}

or:

constraint c_data{N inside {[0:31-7]};}
function void post_randomize();
    data[N+:7]=7'b1111111;
endfunction

The code bellow is wrong:

constraint c_data{N inside {[0:31-7]};data[N+:7]==7'b1111111;}
7

In reply to cainiaoma:

Can someone please explain how this constraint works and generates 7 consecutive ‘ones’.

class Ctrans;
    rand bit[31:0] data;
    rand int N;
    constraint c{data==(7'b1111111 << N);
                 N<32-7;N>=0;}

Thanks

8

In reply to sriharifoxtrot:

See 11.4.10 Shift operators in the 1800-2017 LRM. Then think about the result of that operations for each value of N between 0 and 25.

9

In reply to sriharifoxtrot:

In reply to cainiaoma:
Can someone please explain how this constraint works and generates 7 consecutive ‘ones’.

class Ctrans;
rand bit[31:0] data;
rand int N;
constraint c{data==(7'b1111111 << N);
N<32-7;N>=0;}

Thanks

Understood operators :). Thank you!