How to generate 7 consecutive ones for "rand bit [31:0]:" data variable . Assuming the 7 consecutive ones can occur anywhere in the 32bits

SystemVerilog
,
3

I would try this

rand bit [31:0] data;
rand bit n,m ;  
constraint c{ data[n:m]== 7'd127; } 
constraint range { n <=31 ; n>=7 ; m == n-7 ; }