How to generate 7 consecutive ones for "rand bit [31:0]:" data variable . Assuming the 7 consecutive ones can occur anywhere in the 32bits

SystemVerilog
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8

In reply to sriharifoxtrot:

See 11.4.10 Shift operators in the 1800-2017 LRM. Then think about the result of that operations for each value of N between 0 and 25.