How to generate 7 consecutive ones for "rand bit [31:0]:" data variable . Assuming the 7 consecutive ones can occur anywhere in the 32bits

SystemVerilog
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7

In reply to cainiaoma:

Can someone please explain how this constraint works and generates 7 consecutive ‘ones’.

class Ctrans;
    rand bit[31:0] data;
    rand int N;
    constraint c{data==(7'b1111111 << N);
                 N<32-7;N>=0;}

Thanks