How to generate 7 consecutive ones for "rand bit [31:0]:" data variable . Assuming the 7 consecutive ones can occur anywhere in the 32bits

SystemVerilog
,
6

In reply to ritheshraj:

I try it too.

class Ctrans;
    rand bit[31:0] data;
    rand int N;
    constraint c{data==(7'b1111111 << N);
                 N<32-7;N>=0;}
endclass
module test_top;
    Ctrans trans;
initial begin
    trans=new();
    trans.randomize();
    $display("%b",trans.data);
end
endmodule

This is right.The message printed is “00000000000001111111100000000000”.
I think your constraint of N should be :

N inside {[0:31-7]}

or:

constraint c_data{N inside {[0:31-7]};}
function void post_randomize();
    data[N+:7]=7'b1111111;
endfunction

The code bellow is wrong:

constraint c_data{N inside {[0:31-7]};data[N+:7]==7'b1111111;}