In reply to dave_59:
I tried following code but I am seeing an issue .
Code
class mem_seq_item extends uvm_sequence_item;
//Control Information
rand bit [31:0] data;
rand bit N;
//Utility and Field macros,
uvm_object_utils_begin(mem_seq_item) uvm_field_int(data,UVM_ALL_ON)
uvm_field_int(N,UVM_ALL_ON) uvm_object_utils_end
//Constructor
function new(string name = “mem_seq_item”);
super.new(name);
endfunction
//constaint, to generate any one among write and read
constraint c { data == (7’b1111111 << N ); }
constraint addr_1_range { N inside {[31:0]}; }
endclass
//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
//instance
mem_seq_item seq_item_0;
initial begin
//create method
seq_item_0 = mem_seq_item::type_id::create(“seq_item_0”);
seq_item_0.randomize(); //randomizing the seq_item
seq_item_0.print(); //printing the seq_item_0
end
endmodule
output
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 23: token is ‘\037777777742’
constraint c { data == (7\037777777742\037777777600\037777777631b1111111
<< N ); }