module tb();
bit clk;
always #5 clk++;
property clk_period;
time clk_time, temp;
('1,temp = $time) |=> (clk_time = ($time - temp) && print_time(clk_time));
endproperty
function bit print_time(input time t);
$display("Clock_period:-%0t",t);
return 1;
endfunction
assert property(@(posedge clk)clk_period) $display("Assertion Passed");
else $display("Assertion Failed");
initial
#100 $finish;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
Error message:-
** Error: testbench.sv(11): Illegal assignment to ‘clk_time’ in SVA expression.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.
In reply to markylew:
The syntax for a sequence is
sequence_expr ::=
...
| (sequence_expr {, sequence_match_item}) [sequence_abbrev]
// For example,
(ack, v_data=data, v_ir=ir)[*2]
// in the above case,
(ack // is the (sequence_expr
, v_data=data, v_ir=ir) // is the sequence_match_item
[*2] // is the [sequence_abbrev]
//
// in (ack, v_data=data, v_ir=ir)[*2]
// If ack==true (i.e., evaluates to not zero (e.g., 1) then
// v_data=data, v_ir=ir) is evaluated and that sequence is repeated twice,
// being re-evaluted at every cycle.
// If ack==0, the sequence (of one term in this case) is false.
// in (1,temp = $realtime)
// the "1" is the sequence_expr, and since I always want that to be true, I use "1" instead
// of Variable BBECUSE I WANT temp = $realtime