Clock period using SVA

SystemVerilog
, , ,
3

In reply to cgales:

Hi cgales,
Here is the complete code

module tb();
  
  bit clk;

  always #5 clk++;
  
 
 property clk_period;
   time clk_time, temp;
  
   ('1,temp = $time) |=> (clk_time = ($time - temp) && print_time(clk_time));
     
 endproperty
  
  function bit print_time(input time t);
    $display("Clock_period:-%0t",t);
    return 1;
  endfunction
  
  
  
  
  assert property(@(posedge clk)clk_period) $display("Assertion Passed");
    else $display("Assertion Failed");
  
  

    
  initial 
    #100 $finish;

 initial begin    
 $dumpfile("dump.vcd"); $dumpvars;
 end 
  
endmodule

Error message:-
** Error: testbench.sv(11): Illegal assignment to ‘clk_time’ in SVA expression.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.

EDA Playground Link:-
clock period2 using sva - EDA Playground