Clock period using SVA

SystemVerilog
, , ,
7

In reply to markylew:
The syntax for a sequence is


sequence_expr ::= 
 ...
| (sequence_expr {, sequence_match_item}) [sequence_abbrev]
// For example, 
(ack, v_data=data, v_ir=ir)[*2]
// in the above case, 
(ack // is the (sequence_expr
, v_data=data, v_ir=ir) // is the sequence_match_item 
[*2]  // is the [sequence_abbrev]
//
// in (ack, v_data=data, v_ir=ir)[*2]
// If ack==true (i.e., evaluates to not zero (e.g., 1) then 
//  v_data=data, v_ir=ir)  is evaluated and that sequence is repeated twice, 
//  being re-evaluted at every cycle. 
// If ack==0, the sequence (of one term in this case) is false. 
// in (1,temp = $realtime) 
// the "1" is the sequence_expr, and since I always want that to be true, I use "1" instead 
// of  Variable BBECUSE I WANT temp = $realtime

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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