Hello all I was trying to calculate the time period of clk and trying to print it using assertion. property clk_period; time clk_time, temp; ('1,temp = $time) |=> (clk_time = ($time - temp)&& print_time(clk_time)); endproperty function bit print_time(input time t); $disp…

In reply to SriGanesh D : The correct concepts, coding errors. Also, use realtime. [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. // Code your testbench here // or browse Examples …

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Clock period using SVA

SystemVerilog

Malai_21 September 16, 2020, 1:04am 5

In reply to ben@SystemVerilog.us:

Thank you Ben.