Clock period using SVA

SystemVerilog
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4

In reply to SriGanesh D:
The correct concepts, coding errors.
Also, use realtime.

 
// Code your testbench here
// or browse Examples
module tb();
 
  bit clk;
 
  always #5 clk++;
 
 
 property clk_period;
   realtime clk_time, temp;
 
   (1,temp = $realtime) |=> (1,clk_time = ($realtime - temp))  ##0 (1,print_time(clk_time));
 
 endproperty
 
  function bit print_time(input time t);
    $display("Clock_period:-%0t",t);
    return 1;
  endfunction
  
  assert property(@(posedge clk)clk_period) $display("Assertion Passed");
    else $display("Assertion Failed");
 
  initial 
    #100 $finish;
 
 initial begin    
 $dumpfile("dump.vcd"); $dumpvars;
 end 
 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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