Clock generation through UVC

UVM
, ,
4

In reply to rohitk:

Unfortunately, simulation hang on:

if (clk_on) begin

Have I done something wrong ?

interface clk_if;
	bit clock;
	bit enable;
	bit STARTING_SIGNAL_LEVEL;
	int CLK_HIGH;
	int CLK_LOW;
	
	always begin
		if(enable) begin
			clock = STARTING_SIGNAL_LEVEL;
			#CLK_HIGH;
			clock = ~STARTING_SIGNAL_LEVEL;
			#CLK_LOW;
		end
	end
	
	task start_clock();
		enable = 1'b1;
	endtask: start_clock
	
	task stop_clock();
		enable = 1'b0;
	endtask: stop_clock
endinterface: clk_if