Clock generation through UVC

UVM
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14

In reply to Anudeep J:

You haven’t explained how one controls this clock generation module from any kind of testbench, be it a simple Verilog TB. Is it through module ports, calling tasks, or just setting variables through hierarchical reference?

In most cases, you should be able to use the bind construct to insert a module or interface into your clock generation module that reaches upwards to call tasks, or set variables in that module. For example

module clockgen (output bit clk);
  real period=50/1ns;
  always #(1ns*period/2) clk=!clk;
endmodule

module clockgen_binder;
  function void set_period(real p);
     clockgen.period = p;
  endfunction
endmodule

module tb_top;
...
  bind clockgen clockgen_binder cgb();
...
endmodule

Then read my DVCon paper on how to connect UVM drivers to modules using abstract classes.