In reply to dave_59:
Thanks Dave for the reply.
I will be more clear on my question. I have 10 different interfaces and each interface has a clock signal. All these clocks are driven from a module “clock_generator”. During my simulation, based on some events I have to start some of the clocks, I have to stop some of them or some of the clocks needs frequency change. We have multiple ways of doing it, but Iam looking for a best approach of implementing it, so that I can control them in a simpler way. Control here refers to stopping/starting the specific clock or set of clocks from any uvm_components and top module.