Clock generation through UVC

UVM
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8

In reply to rohitk:
The problem with the always blocks in your interface is that you have a race condition with the driver setting the values to be used as delays. If the always blocks inside the interface start first and enable (or clk_on) are 0, you get into a zero-delay loop and you’ll be stuck in the always block. better to code this as

always begin
        wait(enable)
        clock = STARTING_SIGNAL_LEVEL;
        #CLK_HIGH
        clock = ~STARTING_SIGNAL_LEVEL;
	#CLK_LOW;
    end