Clock generation through UVC

UVM
, ,
6

In reply to rohitk:

I set CLK_HIGH and CLK_LOW in the start_of_simulation phase of my driver as follow:

function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);

    vif.STARTING_SIGNAL_LEVEL = STARTING_SIGNAL_LEVEL;
    vif.CLK_HIGH	= ((NOMINAL_PERIOD/2)*(DUTY_CYCLE/100));
    vif.CLK_LOW		= ((NOMINAL_PERIOD/2)*((1-DUTY_CYCLE)/100));
    /*
    STARTING_SIGNAL_LEVEL, NOMINAL_PERIOD and DUTY_CYCLE come from
    a configuration object
    */
endfunction: start_of_simulation_phase

Nothing is generated in the waveform.