Checker to check the equality of data signals

SystemVerilog
,
1

Hello,

I am stuck at writing a checker that has to verify the following scenario:

Suppose data is sent on a signal A, you have to verify whether the same data is reflected on a signal B exactly after five clock cycles. Also the data can change continuously on signal A every clock cycle. SO your checker should match every data that is sent to Signal A to Signal B.

My initial idea is to use fork…join_any. There will be two statements inside fork…join_any one to check sigA==sigB and other is timeout for 5 cycles. But I am stuck at writing code and also not sure how to account for continuous changes on signal A

Any help please?

PS: I do not want assertions

2

In reply to sandeep1291:
This check is ideal for an assertion. The only reasons for not wanting an assertion for this are probably

  • This is a homework/interview question placing an artificial restriction on the problem.
  • You are using a tool that does not have the assertion feature licensed.
  • The check needs to go inside a class where assertions are not allowed.

I’m going to assume one of the first two. You can do

always @(posedge clk) if ($sampled(B) !=$past(A,5) $error("fail message");

or


always @(posedge clk) pastA <= repeat (5) @(posedge clk) A;
always @(posedge clk) if (B != pastA) $error("fail message");

In either case, you need to deal with startup or reset conditions. I’ll leave that to you.

3

In reply to sandeep1291:

This kind of situation generally occur with the latency in design.
Possible two way to verify:
1). use assertion.
2). use pipelining: store continuous input to temp registers and check appropriate value.
Example:
temp1<=B;
temp2<=temp1;
temp3<=temp2;
.
.
if(!reset)
// don’t check
else
if(a==temp4) // please take-care of latency…
// correct
else
// error

thanks

4

In reply to sandeep1291:

Use automatic tasks to implement the checker as behavioral code. I am also keen as to why no assertions though!

Regards
Srini
www.go2uvm.org

5

In reply to Hardik Vaghela:

I did think of this approach. This will not scale if delay is changed from 5 to 1000 or any huge number. Correct me if I am wrong.

6

In reply to Srini @ CVCblr.com:

Wanted to be comfortable with writing checkers before moving on to using SystemVerilog provided constructs like Assertions.

By the way if I use assertions will this work?

property check_a_b;
    @(posedge clk) disable iff(reset)
     ($rose(a) || $fell(a) || $stable(a))|->##5(a==b);
  endproperty
assert property(check_a_b)else $display("failed");

Thanks

7

In reply to dave_59:

Thank you Dave.
By the way, if I use assertions will the below assertion work as expected?

property check_a_b;
    @(posedge clk) disable iff(reset)
     ($rose(a) || $fell(a) || $stable(a))|->##5(a==b);
  endproperty
assert property(check_a_b)else $display("failed");
8

In reply to sandeep1291:

You need to use local variable. Pseudo-code (Untested):


  // Assuming default clk, disable
  property p_check_a_b;
     int v_a; // same datatype as a
     (!$stable(a), v_a = a)|-> ##5 (v_a==b);
  endproperty : p_check_a_b

 a_p_check_a_b : assert property (p_check_a_b) else `uvm_error("failed");

HTH
Srini
www.verifworks.com

9

In reply to Srini @ CVCblr.com:

Hi Srini,

Thanks for your suggestion. This solution is more intuitive!!

10

In reply to Alonso14:

Quick question related to the things discussed above,

  1. Can i replace the commented line with the following ?? will this satisfy the prob criteria ??
  2. How will this property be evaluated in first 4 cycles ?? as we will not have $past(a,5)

property check_a_b;
    @(posedge clk) disable iff(reset)
     b == $past(a,5);  //   int v_a; 
                       //   (!$stable(a), v_a = a)|-> ##5 (v_a==b);
  endproperty
assert property(check_a_b)else $display("failed");
11

In reply to MLearner:

Hey Mlearner , You need to check the value of b after 5 cycles of occurence of a, so u need to add ##5 tag in consequent. I have modified your code .
module pro_disable;

bit clk;
bit a,b;
bit t = 1;

always #5 clk = ~clk;
always #2 a = ~a;
always #4 b = ~b;

property a1;

@(posedge clk) t |-> ##5 (b==$past(a,5));
endproperty

assert property(a1)else $display("errr in assertion at ",$time);
endmodule