I am stuck at writing a checker that has to verify the following scenario:
Suppose data is sent on a signal A, you have to verify whether the same data is reflected on a signal B exactly after five clock cycles. Also the data can change continuously on signal A every clock cycle. SO your checker should match every data that is sent to Signal A to Signal B.
My initial idea is to use fork…join_any. There will be two statements inside fork…join_any one to check sigA==sigB and other is timeout for 5 cycles. But I am stuck at writing code and also not sure how to account for continuous changes on signal A
This kind of situation generally occur with the latency in design.
Possible two way to verify:
1). use assertion.
2). use pipelining: store continuous input to temp registers and check appropriate value.
Example:
temp1<=B;
temp2<=temp1;
temp3<=temp2;
.
.
if(!reset)
// don’t check
else
if(a==temp4) // please take-care of latency…
// correct
else
// error
Hey Mlearner , You need to check the value of b after 5 cycles of occurence of a, so u need to add ##5 tag in consequent. I have modified your code .
module pro_disable;
bit clk;
bit a,b;
bit t = 1;
always #5 clk = ~clk;
always #2 a = ~a;
always #4 b = ~b;
property a1;
@(posedge clk) t |-> ##5 (b==$past(a,5));
endproperty
assert property(a1)else $display("errr in assertion at ",$time);
endmodule