Checker to check the equality of data signals

SystemVerilog
,
6

In reply to Srini @ CVCblr.com:

Wanted to be comfortable with writing checkers before moving on to using SystemVerilog provided constructs like Assertions.

By the way if I use assertions will this work?

property check_a_b;
    @(posedge clk) disable iff(reset)
     ($rose(a) || $fell(a) || $stable(a))|->##5(a==b);
  endproperty
assert property(check_a_b)else $display("failed");

Thanks