Checker to check the equality of data signals

SystemVerilog
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7

In reply to dave_59:

Thank you Dave.
By the way, if I use assertions will the below assertion work as expected?

property check_a_b;
    @(posedge clk) disable iff(reset)
     ($rose(a) || $fell(a) || $stable(a))|->##5(a==b);
  endproperty
assert property(check_a_b)else $display("failed");