Checker to check the equality of data signals

SystemVerilog
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2

In reply to sandeep1291:
This check is ideal for an assertion. The only reasons for not wanting an assertion for this are probably

  • This is a homework/interview question placing an artificial restriction on the problem.
  • You are using a tool that does not have the assertion feature licensed.
  • The check needs to go inside a class where assertions are not allowed.

I’m going to assume one of the first two. You can do

always @(posedge clk) if ($sampled(B) !=$past(A,5) $error("fail message");

or


always @(posedge clk) pastA <= repeat (5) @(posedge clk) A;
always @(posedge clk) if (B != pastA) $error("fail message");

In either case, you need to deal with startup or reset conditions. I’ll leave that to you.