Checker to check the equality of data signals

SystemVerilog
,
8

In reply to sandeep1291:

You need to use local variable. Pseudo-code (Untested):


  // Assuming default clk, disable
  property p_check_a_b;
     int v_a; // same datatype as a
     (!$stable(a), v_a = a)|-> ##5 (v_a==b);
  endproperty : p_check_a_b

 a_p_check_a_b : assert property (p_check_a_b) else `uvm_error("failed");

HTH
Srini
www.verifworks.com