Checker to check the equality of data signals

SystemVerilog
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10

In reply to Alonso14:

Quick question related to the things discussed above,

  1. Can i replace the commented line with the following ?? will this satisfy the prob criteria ??
  2. How will this property be evaluated in first 4 cycles ?? as we will not have $past(a,5)

property check_a_b;
    @(posedge clk) disable iff(reset)
     b == $past(a,5);  //   int v_a; 
                       //   (!$stable(a), v_a = a)|-> ##5 (v_a==b);
  endproperty
assert property(check_a_b)else $display("failed");