Clock period using SVA

SystemVerilog
, , ,
1

Hello all
I was trying to calculate the time period of clk and trying to print it using assertion.

 property clk_period;
   time clk_time, temp;
  
   ('1,temp = $time) |=> (clk_time = ($time - temp)&& print_time(clk_time));
     
 endproperty
  
  function bit print_time(input time t); 
    $display("Clock_period:-%0t",t);
    return 1;
  endfunction
  
 
  assert property(@(posedge clk)clk_period) $display("Assertion Passed");
    else $display("Assertion Failed");

But always getting error.

2

In reply to SriGanesh D:

Please provide a complete example that demonstrates your error along with the error messages you are receiving.

3

In reply to cgales:

Hi cgales,
Here is the complete code

module tb();
  
  bit clk;

  always #5 clk++;
  
 
 property clk_period;
   time clk_time, temp;
  
   ('1,temp = $time) |=> (clk_time = ($time - temp) && print_time(clk_time));
     
 endproperty
  
  function bit print_time(input time t);
    $display("Clock_period:-%0t",t);
    return 1;
  endfunction
  
  
  
  
  assert property(@(posedge clk)clk_period) $display("Assertion Passed");
    else $display("Assertion Failed");
  
  

    
  initial 
    #100 $finish;

 initial begin    
 $dumpfile("dump.vcd"); $dumpvars;
 end 
  
endmodule

Error message:-
** Error: testbench.sv(11): Illegal assignment to ‘clk_time’ in SVA expression.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.
** Error: testbench.sv(11): Local variable clk_time referenced in expression before getting initialized.

EDA Playground Link:-
clock period2 using sva - EDA Playground

4

In reply to SriGanesh D:
The correct concepts, coding errors.
Also, use realtime.

 
// Code your testbench here
// or browse Examples
module tb();
 
  bit clk;
 
  always #5 clk++;
 
 
 property clk_period;
   realtime clk_time, temp;
 
   (1,temp = $realtime) |=> (1,clk_time = ($realtime - temp))  ##0 (1,print_time(clk_time));
 
 endproperty
 
  function bit print_time(input time t);
    $display("Clock_period:-%0t",t);
    return 1;
  endfunction
  
  assert property(@(posedge clk)clk_period) $display("Assertion Passed");
    else $display("Assertion Failed");
 
  initial 
    #100 $finish;
 
 initial begin    
 $dumpfile("dump.vcd"); $dumpvars;
 end 
 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:
5

In reply to ben@SystemVerilog.us:

Thank you Ben.

6

In reply to SriGanesh D:
In your code,

(1,temp = $realtime) |=> (1,clk_time = ($realtime - temp))  ##0 (1,print_time(clk_time));

can you explain what it’s doing, specifically “(1,temp = $realtime)”?

Thanks

7

In reply to markylew:
The syntax for a sequence is


sequence_expr ::= 
 ...
| (sequence_expr {, sequence_match_item}) [sequence_abbrev]
// For example, 
(ack, v_data=data, v_ir=ir)[*2]
// in the above case, 
(ack // is the (sequence_expr
, v_data=data, v_ir=ir) // is the sequence_match_item 
[*2]  // is the [sequence_abbrev]
//
// in (ack, v_data=data, v_ir=ir)[*2]
// If ack==true (i.e., evaluates to not zero (e.g., 1) then 
//  v_data=data, v_ir=ir)  is evaluated and that sequence is repeated twice, 
//  being re-evaluted at every cycle. 
// If ack==0, the sequence (of one term in this case) is false. 
// in (1,temp = $realtime) 
// the "1" is the sequence_expr, and since I always want that to be true, I use "1" instead 
// of  Variable BBECUSE I WANT temp = $realtime

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers:
8

In reply to ben@SystemVerilog.us:
Thank you Ben.