Topics tagged import

Topic	Replies	Views	Activity
Import package based on define SystemVerilog SystemVerilog , Package , import , define	2	732	March 16, 2023
How UVM knows "my_test" class? why/where do we need to import "my_pkg::*" that holds the class "my_test"? UVM UVM , import , factory , run_test , uvm-package	5	928	June 19, 2022
SystemVerilog include import SystemVerilog SystemVerilog , UVM , Package , import , include	4	2837	April 18, 2018
How to select appropriate package to import with a parameter? SystemVerilog SystemVerilog , parameter , import	3	3775	August 20, 2016
How can I use a DPI C function within a class SystemVerilog SystemVerilog , System-Verilog , import , DPI , imported-c-function	3	7918	March 3, 2016
Declaring timeunit in package SystemVerilog SystemVerilog , Package , import , timeunit	7	6655	August 11, 2014
`include vs import UVM UVM , import , include	4	10810	February 26, 2014