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System verilog macros
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1
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271
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November 29, 2023
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HVL path of uvm_reg for reg.write construction in function
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3
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880
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April 26, 2022
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Assertion macros
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2
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1975
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October 19, 2020
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Creating a timed_wait task
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2
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1394
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February 8, 2019
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Signal direction in function
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4
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2662
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December 15, 2018
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Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock
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7
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10369
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December 26, 2016
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Error - : near "begin": syntax error, unexpected begin, expecting function or task
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1
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4052
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December 14, 2016
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Create my own macros
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2
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1629
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October 19, 2016
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