System verilog macros

UVM
,
1

how was this line work code ? if know means help me about it.

`for(i=0;i < NUM_LANE;i++)
   bit [3:0] powerdown_l`i::; 
`endfor
2

In reply to rajatvlsi:

This is not a SystemVerilog macro. There are a number of separate macro preprocessors this could be from.