Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock

UVM
, ,
1

I create my own my_macros file:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)\
\
`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\	   
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  
			  


`endif  //MY_MACROS_SV

Where mem_type expect string and mem is a member of class.
I got the following compilation error:
at …\sv\my_macros.sv(19): near “:”: syntax error, unexpected ‘:’, expecting IDENTIFIER or clock.

*line 19 is the “default:…”

2

In reply to saritr:

I believe you have got extra \ in your first `define causing confusion to your compiler. Try:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV
 
// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\	   
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  
 
 

`endif  //MY_MACROS_SV

Regards
Srini
www.verifworks.com

3

In reply to Srini @ CVCblr.com:

Now I got:
at …\sv\my_macros.sv(20): near “endcase”: syntax error, unexpected endcase, expecting class.

4

In reply to saritr:

Can you try begin-end around uvm_fatal macro?

`ifndef MY_MACROS_SV
`define MY_MACROS_SV
 
// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)
 
`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\	   
     default: begin `uvm_fatal("FATAL ERROR", "type is not supported") end \ 
     endcase  
 
 
 
`endif  //MY_MACROS_SV

Srini
www.verifworks.com

5

In reply to saritr:

I think you have added space after back-slash. after back-slash nothing is allowed(only new line character allowed). remove spaces after back-slash and try.

6

In reply to jatin.adroja:

Thanks!

7

In reply to Srini @ CVCblr.com:
I changes to the following:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem)\
  begin\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\
    endcase\
  end

`endif  //MY_MACROS_SV

Now I got:
while parsing macro expansion: ‘add_rand’ starting at …\sv\tx_transaction.sv(17)
at …\sv\tx_transaction.sv(17): near “begin”: syntax error, unexpected begin, expecting function or task.

*I called this macro from tx_transaction by:
`add_rand(“int”, mem_int)

8

In reply to saritr:

In case this is not resolved. I tried this code and in works normal on my side


`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)
 
`define add_rand(mem_type)\
  begin\
      case (mem_type)\
       "int":begin  $display("aa"); end\
       "bit": begin $display("bb"); end \
        default:begin `uvm_fatal("FATAL ERROR", "type is not supported")end \
       endcase\
        end 

 
`endif  //MY_MACROS_SV

module test();

initial
`add_rand("int")

endmodule