Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock

UVM
, ,
2

In reply to saritr:

I believe you have got extra \ in your first `define causing confusion to your compiler. Try:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV
 
// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\	   
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  
 
 

`endif  //MY_MACROS_SV

Regards
Srini
www.verifworks.com