Topics tagged RAL

Topic	Replies	Views	Activity
How to learn UVM RAL from basics? UVM UVM , RAL	6	4813	October 4, 2016
Adapter class UVM UVM , RAL	2	4463	September 28, 2016
RAL frontdoor hang UVM UVM , RAL , timeout , fdsq , hang	0	1316	August 8, 2016
RAL UVM UVM , RAL	2	1207	August 8, 2016
Uvm_reg_fifo broken? UVM UVM , RAL , uvm_reg_fifo	1	1401	August 5, 2016
Uvm_config_db get method is failing when null is passed to seq.start() method UVM UVM , RAL , uvm_config_db-get	7	3655	August 4, 2016
Backdoor access is not updating the register in the DUT UVM UVM , RAL , ral-backdoor , UVM_BACKDOOR	1	1625	July 22, 2016
Confused about uvm_mem does not store memory content UVM UVM , RAL , uvm_mem	1	1254	July 20, 2016
Need logic for Burst read /write using RAL model UVM UVM , RAL , BURST	1	1619	July 14, 2016
How to maintain multiple mirror value in a register UVM UVM , RAL , mirror-value	1	1952	May 29, 2016
Driving through RAL UVM UVM , RAL	2	1204	May 29, 2016
RAL UVM UVM , RAL	4	1343	May 17, 2016
Accessing successive numbered registers in SV/UVM UVM UVM , RAL , Cookbook-Registers	0	1382	January 6, 2016
Executing RegModel translation sequence on sequencer, does not have an upstream sequencer defined. Execution of register items available only via direct calls to 'do_rw_access' UVM UVM , RAL , Cookbook-RegistersModelStructure	2	2091	December 9, 2015
I need to know when a W1C register is written UVM UVM , RAL , uvm-register-w1c	0	2526	October 13, 2015
Can one use values from a previously run sequence to constraint a future sequence? UVM UVM , RAL , virtual-sequencer , virtual-sequence , uvm_do_on	1	1431	October 7, 2015
RAL Concept , Benefits? UVM UVM , RAL , uvm_reg_adapter , uvm_reg-frontdoor-backdoor , uvm_reg	2	11013	August 24, 2015
Getting UVM_ERROR for Register Abstraction Layer , But UVM_ERROR's At the end of simulation shown as 0 UVM UVM , RAL	1	1255	August 17, 2015
RAL_model UVM UVM , RAL	0	1388	April 1, 2015
Runtime addition/deletion of Register in RAL Model UVM UVM , RAL , RAL-register-UVM	1	1312	February 25, 2015
Issue in setting up Hdl path in RAL UVM UVM , RAL , unable-to-locate-hdl-path	2	6128	January 9, 2015
Shared address maps in uvm_reg_block UVM UVM , RAL , uvm_reg_block , uvm_reg_map	1	3075	December 24, 2014
Mirror(Difference In Values) UVM UVM , RAL , Register-abstraction-Layer , uvm-register-sequences	4	1888	December 12, 2014
Register Layer Modelling (R.A.L.) Read Data UVM UVM , RAL , Read-Method	1	2123	August 8, 2014
UVM RAL Broadcast write support UVM UVM , RAL , uvm-register , broadcast-writes , aliased-registers	0	1381	May 13, 2014
Can uvm register model which support backdoor operation included in a package? UVM UVM , RAL , Package , uvm_reg-frontdoor-backdoor , hierarchy-reference	2	1579	May 1, 2014
Special register(s) with fields based on a mode UVM UVM , registers , RAL , uvm-register , uvm_reg_block	0	1748	April 16, 2014
RAL UVM_ERROR: get: unable to locate hdl path mem_dut.mem[5] # Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM UVM , RAL	3	4334	March 21, 2014
RAL ERROR reporter [RegModel] map 'mem_map' does not seem to be initialized correctly UVM UVM , RAL	1	3167	March 14, 2014
Merging all register cover objects into one object UVM UVM , Coverage , cover-groups , RAL	1	2388	January 30, 2014