I have understood how RAL is used in UVM .
But still I am not clear about the benefits of using RAL .
Point 1.) Backdoor access can be done using the hierarchical path without RAL then how RAL can be of more benefit ?
Point 2.) Register write/read through front door will take same time in case of uvm_re_seq or normal uvm_seq . So what is benefit of RAL for front door access ?
Point 3.) For using RAL , reg block and uvm_reg have to be created which seems an extra burden of writing code .
Point 4.) Firmware level abstraction of stimulus (i.e. Set this bit in this register rather than write x to address y):
but this can be done using normal uvm_sequence
Point 5.) Stimulus reuse (If the bus agent changes, the stimulus still works) :
if bus width and signals changes then changes will have to be made in RAL model also then how reusability ?
Point 6.) Why address map for the same physical register in DUT , will be different for different interfaces ?
Point 7.) If RAL is used then will there be two scoreboards and two coverage class , one for normal bus transaction and other for reg items .
Point 8.) How write /read for SDRAM can be implemented using RAL (because row and column address will be required for access)
Basically , It seems to me that efforts in using RAL is more than benefits .
My understanding may be wrong for some things , please correct me if I am wrong somewhere and try to explain benefits considering practically aspects .
While it’s true that you can do the job without using a register abstraction layer, this doesn’t mean you won’t benefit from using one. What it provides is a nice way of centralizing all register verification aspects, such as applying stimulus, checking and collecting coverage.
Let’s go through your questions one by one.
Using hierarchical paths isn’t directly possible from packages, so you won’t be able to use sequences or the such to do it.
I don’t really get what you mean by this one. How long a transaction takes isn’t a function of the way you insert it, but a function of the DUT you verify. Of course they’re going to take the same amount of time.
If you don’t write this code, you’re going to have to write your sequences in such a way as to avoid magic numbers (address 0x1234 or whatever where some important register is mapped).
You can do this only with sequences, but you won’t benefit from automated checks by having a register model.
Why should there changes need to be made in the register model? It’s completely agnostic of the bus you access your registers.
Because the same register could be mapped at different addresses when accessing it through different interfaces. No one is stopping you from using the same address map for multiple interfaces if that’s not the case.
Checks for registers are already provided by the register model. I don’t see why there would be two scoreboards. You would have different coverage classes, but that’s not a big deal, since you’re just moving aspects from one to the other.
I’m pretty sure that row/column address come from one “big” address, because from a programmer’s point of view, RAM is mapped as contiguous locations each with its own address (and not as a matrix).
RAL is mainly use for standardization. Of course, you can build your own one but it is used only for yourself. Your questions are already answered by Tudor, so I just add my opinions to them.
Backdoor access is using VPI. To understand VPI and use it correctly is more complicated than RAL’s DPI.
To user perspective, changing registers’ value and updating them to DUT is much more simple and straight forward than calling sequences.
RAL benefits are at scoreboard and checking model. If you want to verify all functions of the DUT, sooner or later you will have to implement all registers.
Same to 2.
Agree with Tudor. RAL is another abstract level, any changes at the interface should not affect it.
Agree with Tudor.
Scoreboard and coverage are depended on the pass condition. So they are your responsibility and decision, not RAL.
Agree with Tudor. Usually you will have a SDRAM controller to access to SDRAM.
I’m not a native English speaker. Sorry for my bad English :)