Confused about uvm_mem does not store memory content

UVM
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I’m reading the UVM RAL cookbook and I came to this section about uvm_mem. It says there that unlike uvm_reg, uvm_mem does not store the state or the memory content due to simulation overhead. From what I understand, it cannot store write_data to the memory addresses. So now I’m confused because the uvm_mem::write() method has input data as an argument to it and the uvm_mem::read() method has output data that gives back the read data on the memory location… One more thing is, if we cannot write data to the memory, then how can we verify if that portion of the memory is actually working?

Am I misunderstanding that section of the cookbook?
Thanks.

Regards,
Reuben

2

In reply to Reuben:

They are saying that the register model does not maintain mirrored values for uvm_mem. You can still perform a write() and read() to the memories in your design (same as a register wr/rd).