In reply to ben@SystemVerilog.us:
Assertions are written to express requirements. I don’t see a difference in expressing that a delay should not be less than or equal to5 cycles and delay should be greater or equal to 5 cycles. Where is the INCOMPLETION? An assertion is incomplete if you have not provided enough cycles in the simulation to complete.
If you see the property written as “should be >= than”, it won’t finish until first_match(~) is found.
In the following cases, the property would not become completed because there are no more my_seq following.****
- my_seq is issued only once during the simulation.
- 10 consecutive my_seq issued. (Focus on the last my_seq issued.)
Since above two scenarios are not out of the specification, I shouldn’t put strong in the property to get errors on incompletion.
But in the case the property is written as “should not be < than”, the property will be completed my_timing cycles after the point it is enabled.
I am starting to think that getting incomplete assertions would not matter much.
I just thought it can be written more efficiently.
Please correct me if I am thinking it the wrong way.
Thanks.