In reply to Jung Ik Moon:
If you have a signal that can be used as a trigger to identify an upcoming end of the simulation, you can use that with an assertion control or part of the disabling condition (like in a default disable) to stop the checking of assertions. From my book: .
The $assertcontrol provides finer granularity in how and which types of assertions are controlled. The syntax is repeated below:
$assertcontrol ( control_type [ , [ assertion_type ] [ , [ directive_type ]
[ , [ levels ] [ , list_of_scopes_or_assertions ] ] ] ] ) ;
let OFF = 4; // assertion control type
// Assertion directives
let ASSERT = 1; // directive_type for assertion control tasks
let COVER = 2; // directive_type for assertion control tasks
let ASSUME = 4; // directive_type for assertion control tasks
let ALL_DIRECTIVES = (ASSERT|COVER|ASSUME); // (i.e., 7)
let ALL_ASSERTS = (CONCURRENT|S_IMMEDIATE|D_IMMEDIATE|EXPECT); // (i.e., 31)
/* The OFF control stops the checking of all specified assertions until a subsequent
$assertcontrol with a control_type of 3 (On). No new attempts will be started. Attempts that are already executing for the assertions, and their pass or fail statements, are not affected. Any queued or pending assertions are not flushed and may still mature. No new instances of assertions are queued. The assertions are re-enabled with a subsequent $assertcontrol with a control_type of 3 (On).
This control_type value does not affect expect statements. For example,*/
$assertcontrol(OFF); // using default values of all other arguments
$assertcontrol(LOCK, ALL_ASSERTS, ALL_DIRECTIVES, 0, ap_x1); // lock any changes to ap_x1
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115