Using "not" in SystemVerilog Assertions

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Some more questions on your answer.

[list=3][*] The use of not of a sequence can be confusing. Why not making it a positive type of requirement. Thus instead of

  • “my_seq to my_seq delay should not be less than my_timing.”, use
  • “my_seq to my_seq delay should be >= than my_timing.”

[/list]

  1. By modifying “should not be < than” to “should be >= than”, isn’t it more likely to become an incomplete assertion at the end of the simulation?
  2. How should I interpret incomplete assertions in this case? Can I just say it PASSED?
  3. Is is possible to write a property sticking to “should not be < than”? This is just to solve the incompletion issue, IF needed.
  • 4. i.e., “when my_seq is issued, my_seq cannot be issued within my_timing.”

Thanks and Regards,
Jung Ik Moon