Using Multi-clocked intersect operator

SystemVerilog
,
2

In reply to MICRO_91:
**Requirement is that that when ‘en’ is high , ‘ip_clk’ shouldn’t toggle till ‘en’ is de-asserted .**y
Whenever I encounter a tricky requirement, particularly when clocks are involved, I start with a task model and then see if can convert it to an SVA assertion.


    task automatic t(); 
      // bit ip_clk_toggle; // Initial thoughts
      //                     but that is not panning to anything useful  
      // fork
      //   @(negedge en) //  ip_clk can toggle 
      // join_any
       fork
         @(ip_clk)  // If ip_clk is toggling, then en must be==0
         #1; // The #1 is needed if en changes in the NBA region of ip_clk
         am_ip_clk: assert final (en==0);
       join
    endtask

    always @(posedge global_clk) begin //  ip_clk  is  much higher frequency than global_clk
        fork t(); join_none        
    end

You can tune this model as needed.
I do not see an easy path to model these requirements into straight SVA.
The task model is structured around my paper Understanding the SVA Engine Using the Fork-Join Model

Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

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