In reply to ben@SystemVerilog.us:
After some thoughts, you can convert the task approach to SVA.
// Best Option: if en then no toggling
ap_ipclk_en1: assert property(
@(posedge global_clk) (en) |=> // clock switch
@(ip_clk) 1[*N] en==0); // If ip_clk is toggling, then en must be==0
// Another option
// when 'en' is high , 'ip_clk' shouldn't toggle till 'en' is de-asserted .
let N=2; // to allow for a few ip_clk edges to occur before checking for the en
ap_ipclk_en0: assert property(
@(posedge global_clk) 1 ##1 // clock switch
@(ip_clk) 1[*N] en==0); // If ip_clk is toggling, then en must be==0
// more simply
always(@(ip_clk) assert(en==0);
//
Ben