In reply to ben@SystemVerilog.us:
Hi Ben ,
Whenever I encounter a tricky requirement, particularly when clocks are involved, I start with a task model and then see if can convert it to an SVA assertion.
I agree , having referred to your response , I have a task based solution ( using immediate assertion ) which uses SV constructs.
I was wondering if I could achieve the same using concurrent assertion.
Since I was trying a few codes , I have a question related to intersect operator :
Can the RHS N LHS of intersect operator have different clocks ? i.e can we have a multi-clocked intersect operator ?
I am aware that multi-clocked or/and operator are legal ( assuming there is a single leading clock )