Using Multi-clocked intersect operator

SystemVerilog
,
6

In reply to ben@SystemVerilog.us:

Hi Ben ,
(1)

After some thoughts, you can convert the task approach to SVA.
// Best Option: if en then no toggling


ap_ipclk_en1: assert property( @(posedge global_clk) (en) |=>  @(ip_clk) 1 ##0 ( !en ) ); 


Thanks , this works

(2)

Sometimes, the best way to get such answers is to try it out; in general, and hopefully, the vendors know 1800 better than any of us.

I did try it out , I run into a compilation error : edalink

I was going through LRM Section 16.9.6 and 16.13.2 but I don’t see multi-clocked intersect operator as illegal . Since multi-clocked and/or operator are legal within a property , why isn’t multi-clocked intersect operator legal ?