Using Multi-clocked intersect operator

SystemVerilog
,
8

In reply to ben@SystemVerilog.us:

Because the lengths of the two matches of the operand sequences cannot be guaranteed to be the same.

I see your point .
and / or operator do not have the requirement that the lengths of the LHS and RHS be the same , hence and / or operator can have non-identical clocks in LHS and RHS.

I tried using throughout operator :


 property  inter_sect ;
   not( @( ip_clk ) 1 ) throughout  @(posedge global_clk) ( $fell( en ) [->1] );  
  endproperty

As the LHS of throughout operator can’t be temporal , I observe compilation error

So to summarize multi-clocked properties are only valid for and/or/not operators,
i.e the LHS and RHS can have non-identical clocks

Have another question :

Also, your example not( @( ip_clk ) 1 ) intersect @(posedge global_clk) ( $fell( en ) [->1] ); has a property_expr intersect sequence_expr, which is illegal.

Why is $fell( en )[->1] considered a sequence_expression ?
As the intersect operator is written within a property , won’t it consider RHS as property automatically ?