Using Multi-clocked intersect operator

SystemVerilog
,
13

In reply to MICRO_91:
The toughout operator specifies that a signal (expression) must hold throughout a sequence. *( b throughout R ) is equivalent to ( b [0:$] intersect R )
Multiclocking is illegal for your reason 2

Add the implies


 assert property(@(posedge clk1) 1 |-> @(posedge clk1) a implies  @(posedge clk2) b);  
    // assert property(@(posedge clk1) a implies @(posedge clk2) b); // illegal, No LCE
// LCE Leading Clocking Event

Ben