In reply to Michael54:
I’d not say frontdoor access is more easy to implement. You have to provide the bus2reg and reg2bus functions in the adapter. This is more effort then defining the HDL path. And frontdor access uses bus cyles to access the registers, i.e. it needs more clock cycles. But it is not slowing down the simulation.
backdoor access is the only way to deal with access limitations of the registers, like RO/WO registers.
Nobody is saying backdoor is the ultimate way to access registers. But there is an abolute need to have it.