In the following code I am trying use the assertion in the way that when the signal_a == 1 and signal_b == 0, within 6 clock cycle the frequency of clka, clkb and clkc are calculate and compare with each other! Any idea what did I miss? PS. The code compile and run but never calculate frequency/period and shows always as 0. The clka, clkb and clkc are changing over simulation!
module assertions_module (
input logic signal_a,
input logic signal_b,
input logic clkc,
input logic clka,
input logic clkb
);
real clka_freq;
real clkb_freq;
real clkc_freq;
task automatic freq_meter(input logic clk_in, ref real clk_out_freq);
time start_time, end_time;
time period;
real clk_freq;
@(posedge clk_in);
start_time = $time;
@(posedge clk_in);
end_time = $time;
period = end_time - start_time;
clk_freq = real'(1e12/period);
clk_out_freq = clk_freq/1e6;
endtask : freq_meter
task automatic all_clk_freq_meter();
@(posedge clka)
freq_meter(clka, clka_freq);
@(posedge clkb)
freq_meter(clkb, clkb_freq);
@(posedge clkc)
freq_meter(clkc, clkc_freq);
endtask: all_clk_freq_meter
always_comb
begin
clka_test_assert: assert property(
@(posedge clka)
signal_a && !signal_b |-> ##[0:6] (1, all_clk_freq_meter()) ##1 (clka_freq != clkc_freq));
clkb_test_assert: assert property(
@(posedge clkb)
signal_a && !signal_b |-> ##[0:6] (1, all_clk_freq_meter()) ##1 (clkb_freq == clkc_freq));
end
endmodule