In reply to ben@SystemVerilog.us:
Thank you so much @Ben for your time.
A question I have;
In the line @(posedge clka) am_ac: if(clka_freq != clkc_freq) ac_match=1;
if(clkb_freq == clkc_freq) bc_match=1;
we just consider the clka as well as here
always @(posedge clka) // Fire the tasks to compute the frequencies
clk_test_assert: assert property(
!active && signal_a && !signal_b |-> (1, all_clk_freq_meter()));
Should I do the same for clkb, or either one should fulfil my requirements!?
I believe you tried to combine 2 clka_test_assert and clkb_test_assert in the 1 assertion, if so, what should I do if 2 assertion conditions is different like:
always_comb
begin
clka_test_assert: assert property(
@(posedge clka)
signal_a && !signal_b |-> ##[0:6] (1, all_clk_freq_meter()) ##1 (clka_freq != clkc_freq));
clkb_test_assert: assert property(
@(posedge clkb)
!signal_a || (!signal_b && signal_c) |-> ##[0:6] (1, all_clk_freq_meter()) ##1 (clkb_freq == clkc_freq));
end
I should add that the problem that the clocks frequencies are equal to zero.
I tried to put several displays in the task, but it seems that it is not called at all.