In reply to ben@SystemVerilog.us:
Hey Ben,
I tried to simplified my question to get an idea about the process.
My main requirement is as follow:
module assertions_module (
input logic signal_1,
input logic signal_2,
input logic signal_3,
input logic signal_4,
input logic signal_5,
input logic clka,
input logic clkb,
input logic clkc
);
real clka_freq;
real clkb_freq;
real clkc_freq;
logic clka_t;
logic clkb_t;
logic clkc_t;
task automatic freq_meter(ref logic clk_in, ref real clk_freq);
time start_time, end_time;
time period;
@(posedge clk_in);
start_time = $time;
@(posedge clk_in);
end_time = $time;
period = end_time - start_time;
clk_freq = real'(1e12/period);
clk_freq = clk_freq/1e6;
endtask : freq_meter
// I am using following 3 always because when use ref for input of freq_meter it says Variable input ports cannot be driven
always @(posedge clka)
clka_t <= clka;
always @(posedge clkb)
clkb_t <= clkb;
always @(posedge clkc)
clkc_t <= clkc;
task automatic start_measurement();
active <= 1;
repeat(6) begin
fork
@(posedge clka_t)
freq_meter(clka_t, clka_freq);
@(posedge clkb_t)
freq_meter(clkb_t, clkb_freq);
@(posedge clkc_t)
freq_meter(clkc_t, clkc_freq);
join
@(posedge clka_t)
if(clka_freq == clkc_freq)
clka_match = 1;
@(posedge clkb_t)
if(clkb_freq == clkc_freq)
clkb_match = 1;
end
clka_match_assert: assert(clka_match == 1);
clkb_match_assert: assert(clkb_match == 1);
clka_match = 0;
clkb_match = 0;
active = 0;
endtask : start_measurement
always @(posedge clka_t)
clka_assert1: assert property(
!active && signal_1 && !signal_2 && signal_3 |-> (1, start_measurement()));
always @(posedge clkb_t)
clkb_assert1: assert property(
!active && signal_4 && !signal_2 && signal_5 |-> (1, start_measurement()));
always @(posedge clka_t)
clka_assert2: assert property(
!active && !signal_1 && signal_2 |-> (1, start_measurement()));
always @(posedge clkb_t)
clkb_assert2: assert property(
!active && !signal_4 && signal_2 |-> (1, start_measurement()));
this |-> (1, start_measurement()) means the task start_measurement() always call regardless of left side of |-> ?
In either case the condition never met and I don’t see the assertion/start_measurement/freq_meter call at all.