In reply to MahD:
The problem was that the task waited for the @(posedge clk_in) start_time = $time;
I replicated the procedure and used the input clocks directly.
Now it works.
module assertions_module (
input logic signal_1,
input logic signal_2,
input logic signal_3,
input logic signal_4,
input logic signal_5,
input logic clka,
input logic clkb,
input logic clkc
);
bit active;
bit debug;
// Compute the clock frequency
task automatic freq_metera(ref real clk_freq);
time start_time, end_time;
time period;
@(posedge clka) start_time = $time;
@(posedge clka) end_time = $time;
period = end_time - start_time;
clk_freq = real'(1e12/period);
clk_freq = clk_freq/1e6;
endtask : freq_metera
task automatic freq_meterb(ref real clk_freq);
time start_time, end_time;
time period;
@(posedge clkb) start_time = $time;
@(posedge clkb) end_time = $time;
period = end_time - start_time;
clk_freq = real'(1e12/period);
clk_freq = clk_freq/1e6;
endtask : freq_meterb
task automatic freq_meterc(ref real clk_freq);
time start_time, end_time;
time period;
@(posedge clkc) start_time = $time;
@(posedge clkc) end_time = $time;
period = end_time - start_time;
clk_freq = real'(1e12/period);
clk_freq = clk_freq/1e6;
endtask : freq_meterc
// Do the measument 6 times, but break if a pass within the 6 cycles
task automatic start_measurement();
real clka_freq, clkb_freq, clkc_freq;
bit passa, passb;
active = 1; //#2 active=0; // debug
debug =1;
repeat(6) begin : try6
fork
@(posedge clka) freq_metera(clka_freq);
@(posedge clkb) freq_meterb(clkb_freq);
@(posedge clkc) freq_meterc(clkc_freq);
join
@(posedge clka);
clka_match_assert: assert(clka_freq == clkc_freq) passa=1;
clkb_match_assert: assert(clkb_freq == clkc_freq) passb=1;
debug =1; #3 debug=0;
if(passa && passb) break;
end
active <= 0;
endtask : start_measurement
clka_assert1: assert property(@(posedge clka)
!active && signal_1 && !signal_2 && signal_3 |-> (1, start_measurement()));
clkb_assert1: assert property( @(posedge clkb)
!active && signal_4 && !signal_2 && signal_5 |-> (1, start_measurement()));
clka_assert2: assert property(@(posedge clka)
!active && !signal_1 && signal_2 |-> (1, start_measurement()));
clkb_assert2: assert property(@(posedge clkb)
!active && !signal_4 && signal_2 |-> (1, start_measurement()));
endmodule
module tb;
timeunit 1ns;
timeprecision 100ps;
logic clkc = 0;
logic clka = 0;
logic clkb = 0;
logic signal_1, signal_2, signal_3, signal_4, signal_5;
always #5 clkc = ~clkc;
always #10 clka = ~clka;
always #20 clkb = ~clkb;
initial #5000 $finish;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#150 signal_1 = 0; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
#200 signal_1 = 0; signal_2 = 0; signal_3 = 1; signal_4 = 1; signal_5 = 1;
#250 signal_1 = 1; signal_2 = 1; signal_3 = 0; signal_4 = 1; signal_5 = 1;
#300 signal_1 = 1; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
#350 signal_1 = 1; signal_2 = 0; signal_3 = 1; signal_4 = 0; signal_5 = 1;
#400 signal_1 = 0; signal_2 = 1; signal_3 = 0; signal_4 = 0; signal_5 = 1;
#450 signal_1 = 0; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
#500 signal_1 = 0; signal_2 = 0; signal_3 = 0; signal_4 = 1; signal_5 = 1;
$stop ;
end
assertions_module assertions_module_inst(
.signal_1(signal_1),
.signal_2(signal_2),
.signal_3(signal_3),
.signal_4(signal_4),
.signal_5(signal_5),
.clka(clka),
.clkb(clkb),
.clkc(clkc)
);
endmodule